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NOIL1SN3000A
ADC and LVDS Channel Powerdown Registers (b1000010-
1000110 / d66-70)
Each of the 32 data channels, sync, and clock out LVDS
channels are individually powered down by setting the
Table 43. MISC1 SUPERBLK CONTROL REGISTER
Value Effect
crc_en, bit <0>
appropriate bits of these registers. Powering down a channel
stops the clock for the odd and even ADCs and LVDS
serializer, and turns off the LVDS output driver. Note that the
enable pwd_ena in register d71 is set for these bits to take
affect. Bits 31:0 are used for data channels 31:0 respectively.
0
1
On startup
No CRC words inserted
CRC words inserted into the data stream
Normal operation
1
Setting bit 33 powers down the output clock channel; bit 32
crc_sync_en, bit<1>
powers down the sync channel. Setting a particular bit high
brings the selected channel to its power down mode.
Table 42. PWD_CHAN<33:0>
0
1
No CRC words inserted
Normal operation
Crc words inserted into the sync channel
Value bit<x>
Effect
On startup
0
0
Normal operation
pwd_ena, bit<2>
1
On startup
Channel powered down
0
0
1
Per channel power down disabled
Normal operation
Enable per channel power down
Misc1 SuperBlk Control Register (b1000111 / d71)
On startup
0
The misc1 superblk control register contains several
control and test enable bits. The superblk refers to the AFE,
ADC, CRC, Serialization, and LVDS channels and
supporting controls.
? crc_en, bit <0> . This bit enables inserting CRC words
into the data channels at the end of a row of image data.
pwd_glob, bit<3>
0 Normal operation
1 Power down all channels
On startup 0
test_en, bit<4>
Protocol Layer on page 12 contains more details on this
protocol.
? crc_sync_en, bit<1> : This bit enables inserting CRC
words into the sync channel. This is generally not
0
1
On startup
Normal operation
Test Mode
0
desired.
? pwd_ena, bit<2> . This bit provides the ability to
power down individual channels through the pwd_chan
registers.
? pwd_glob, bit<3> . This bit, when set, globally powers
down all 32 data channels, the sync channel, and the
atst_en, bit<5>
0 Normal operation
1 ADC analog test mode
On startup 0
sblk_spare1, bit<6>
clock out channel. This overrides the per channel power
0
Normal operation
down controls.
? test_en, bit<4> . This bit is provided to test the serial
LVDS output drivers. When set, the LVDS output clock
is routed to all output data channels. This is intended
for debug and testing only.
? atst_en, bit<5> . This bit enables driving an external
analog input voltage to the 64 ADCs for testing. When
set, the external pin Analog_in and Vdark reference are
1
On startup 0
sblk_spare2, bit<7>
0
1 Normal operation
On startup 1
sent to all ADCs.
? sblk_spare1, bit<6> . This bit is a spare control bit. It is
set to 0 at POR.
? sblk_spare2, bit<7> .: This bit is a spare control bit. It
is set to 1 at POR.
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